1. Field of the Invention
The present invention relates to the manufacture of integrated circuits by a lithographic process and, in particular, to a method and system for determining critical dimension or overlay variation of integrated circuit fields within and between chip levels and layers.
2. Description of Related Art
Semiconductor integrated circuit manufacturing requires the sequential patterning of process levels on a single semiconductor wafer. Exposure tools print multiple integrated circuit patterns or fields by lithographic methods on successive levels of the wafer. These tools typically pattern the different levels by applying step and repeat lithographic exposure or step and scan lithographic exposure in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits. Typically, 20-50 levels are required to create an integrated circuit. In some cases, multiple masks are required to pattern a single level.
Successful fabrication of integrated circuit devices requires the precise and accurate measurements of registration of the mask (reticle) set and overlay placement of mask level to subsequent mask level. Current manufacturing technology uses separate methods of measuring mask registration and wafer level overlay. The use of bar in bar (box in box) and grating targets only allows for the measurement of overlay on the wafer level with no information of mask registration information. Current technology has limited application due to size restriction for placement around the mask reticle field. These targets are also greatly affected by process induced variations given that they are not within the shape pattern densities found within the functioning chip. Hence, these targets are susceptible to chemical mechanical planarization, thermal processing, and lithography image processing.